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93C76/86
8K/16K 5.0V Microwire(R) Serial EEPROM
FEATURES
* Single 5.0V supply * Low power CMOS technology - 1 mA active current typical * ORG pin selectable memory configuration 1024 x 8- or 512 x 16-bit organization (93C76) 2048 x 8- or 1024 x 16-bit organization (93C86) * Self-timed ERASE and WRITE cycles (including auto-erase) * Automatic ERAL before WRAL * Power on/off data protection circuitry * Industry standard 3-wire serial I/O * Device status signal during ERASE/WRITE cycles * Sequential READ function * 1,000,000 ERASE/WRITE cycles guaranteed * Data retention > 200 years * 8-pin PDIP/SOIC package * Temperature ranges supported - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C - Automotive (E) -40C to +125C
PACKAGE TYPES
DIP Package
CS CLK DI DO
1 2 3 4
8 7 6 5
VCC PE ORG VSS
93C76/86
SOIC Package 1 2 3 4 8 7 6 5
93C76/86
CS CLK DI DO
VCC PE ORG VSS
BLOCK DIAGRAM
VCC VSS
DESCRIPTION
The Microchip Technology Inc. 93C76/86 are 8K and 16K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power non-volatile memory applications. These devices also have a Program Enable (PE) pin to allow the user to write protect the entire contents of the memory array. The 93C76/86 is available in standard 8-pin DIP and 8pin surface mount SOIC packages.
Memory Array
Address Decoder
Address Counter
Data Register
DI
Output Buffer
DO
PE CS
Mode Decode Logic
CLK
Clock Generator
Microwire is a registered trademark of National Semiconductor Incorporated.
(c) 1998 Microchip Technology Inc.
DS21132D-page 1
93C76/86
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name CS CLK DI DO VSS ORG PE VCC
PIN FUNCTION TABLE
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memory Configuration Program Enable Power Supply
VCC ...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V Storage temperature ..................................... -65C to +150C Ambient temp. with power applied................. -65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability
1.2
AC Test Conditions
AC Waveform: VLO = 2.0V VHI = Vcc - 0.2V VHI = 4.0V for (Note 1) (Note 2)
Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For VCC > 4.0V 0.5 VCC 0.5 VCC
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +4.5V to +5.5V Commercial (C): Tamb = 0C to -40C Industrial (I): Tamb = -40C to +85C Automotive (E): Tamb = -40C to +125C Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Symbol VIH1 VIL1 VOL1 VOL2 VOH1 VOH2 ILI ILO CINT ICC write ICC read ICCS Min. 2.0 -0.3 -- -- 2.4 VCC-0.2 -10 -10 -- -- -- -- Max. VCC +1 0.8 0.4 0.2 -- -- 10 10 7 3 1.5 100 Units V V V V V V A A pF mA mA A Conditions -- -- IOL = 2.1 mA; VCC = 4.5V IOL =100 A; VCC = 4.5V IOH = -400 A; VCC = 4.5V IOH = -100 A; VCC = 4.5V. VIN = 0.1V to VCC VOUT = 0.1V to VCC (Note) Tamb = +25C, FCLK = 1 MHz FCLK = 2 MHz; VCC = 5.5V FCLK = 2 MHz; VCC = 5.5V CLK = CS = 0V; VCC = 5.5V DI = PE = VSS ORG = VSS or VCC
Note:
This parameter is periodically sampled and not 100% tested.
DS21132D-page 2
(c) 1998 Microchip Technology Inc.
93C76/86
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +4.5V to +5.5V Commercial (C): Tamb = 0C to -40C Industrial (I): Tamb = -40C to +85C Automotive (E): Tamb = -40C to +125C Parameter Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time Symbol FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH TPD TCZ TSV TWC TEC TWL -- Min. -- 300 200 50 0 250 100 100 -- -- -- -- -- -- 1M Max. 2 -- -- -- -- -- -- -- 400 100 500 10 15 30 -- Units MHz ns ns ns ns ns ns ns ns ns ns ms ms ms cycles Conditions Vcc 4.5V
Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL = 100 pF (Note 1) CL = 100 pF ERASE/WRITE mode (Note 2) ERAL mode WRAL mode 25C, VCC = 5.0V, Block Mode (Note 3)
Endurance
Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical program cycle is 4 ms per word. 3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
(c) 1998 Microchip Technology Inc.
DS21132D-page 3
93C76/86
TABLE 1-4:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C76: ORG=1 (X16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXX X A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXX X A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXX 00XXXXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 29 13 13 13 29 29 13
TABLE 1-5:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C76: ORG=0 (X8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXXX X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXXX X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXXX 00XXXXXXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 22 14 14 14 22 22 14
TABLE 1-6:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C86: ORG=1 (X16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 X X X X X XXX A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X XXX A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXX 00XXXXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 29 13 13 13 29 29 13
TABLE 1-7:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C86: ORG=0 (X8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXXX A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXXX A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXXX 00XXXXXXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 22 14 14 14 22 22 14
DS21132D-page 4
(c) 1998 Microchip Technology Inc.
93C76/86
2.0 PRINCIPLES OF OPERATION
2.3
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high impedance state on the falling edge of the CS.
Erase/Write Enable and Disable (EWEN, EWDS)
The 93C76/86 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.
2.1
START Condition
2.4
Data Protection
The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected.
During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.
(c) 1998 Microchip Technology Inc.
DS21132D-page 5
93C76/86
3.0
3.1
DEVICE OPERATION
READ
3.4
Erase All (ERAL)
The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit (x16 organization) or 8 bit (x8 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high and clock transitions continue. The memory address pointer will automatically increment and output data sequentially.
The ERAL instruction will erase the entire memory array to the logical "1" state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences on the rising edge of the last address bit (A0). Note that the least significant 8 or 9 address bits are don't care bits, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at Vcc = +4.5V to +5.5V. The DO pin indicates the READY/BUSY status of the device if the CS is high. The READY/BUSY status will be displayed on the DO pin until the next start bit is received as long as CS is high. Bringing the CS low will place the device in standby mode and cause the DO pin to enter the high impedance state. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the entire device has been erased and is ready for another instruction. The ERAL cycle takes 15 ms maximum (8 ms typical).
3.2
ERASE
The ERASE instruction forces all data bits of the specified address to the logical "1" state. The self-timed programming cycle is initiated on the rising edge of CLK as the last address bit (A0) is clocked in. At this point, the CLK, CS, and DI inputs become don't cares. The DO pin indicates the READY/BUSY status of the device if the CS is high. The READY/BUSY status will be displayed on the DO pin until the next start bit is received as long as CS is high. Bringing the CS low will place the device in standby mode and cause the DO pin to enter the high impedance state. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been erased and the device is ready for another instruction. The ERASE cycle takes 3 ms per word (Typical).
3.5
Write All (WRAL)
3.3
WRITE
The WRITE instruction is followed by 16 bits (or by 8 bits) of data to be written into the specified address. The self-timed programming cycle is initiated on the rising edge of CLK as the last data bit (D0) is clocked in. At this point, the CLK, CS, and DI inputs become don't cares. The DO pin indicates the READY/BUSY status of the device if the CS is high. The READY/BUSY status will be displayed on the DO pin until the next start bit is received as long as CS is high. Bringing the CS low will place the device in standby mode and cause the DO pin to enter the high impedance state. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been written and the device is ready for another instruction. The WRITE cycle takes 3 ms per word (Typical).
The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences on the rising edge of the last address bit (A0). Note that the least significant 8 or 9 address bits are don't cares, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guaranteed at Vcc = +4.5V to +5.5V. The DO pin indicates the READY/BUSY status of the device if the CS is high. The READY/BUSY status will be displayed on the DO pin until the next start bit is received as long as CS is high. Bringing the CS low will place the device in standby mode and cause the DO pin to enter the high impedance state. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the entire device has been written and is ready for another instruction. The WRAL cycle takes 30 ms maximum (16 ms typical).
DS21132D-page 6
(c) 1998 Microchip Technology Inc.
93C76/86
FIGURE 3-1:
CS VIH VIL CLK VIH VIL DI VIH VIL DO (Read) VOH VOL TSV STATUS VALID TPD TPD TCZ TCZ TDIS TDIH TCSS TCKH TCKL TCSH
SYNCHRONOUS DATA TIMING
VOH DO (Program) VOL
The memory automatically cycles to the next register. FIGURE 3-2:
CS
READ
TCSL
CLK
DI
1
1
0
AN
...
A0
DO
HIGH IMPEDANCE
0
DN
...
D0
DN
...
D0
FIGURE 3-3: EWEN
CS
EWEN
TCSL
CLK ...
ORG=VCC, 8 X's ORG=VSS, 9 X's
DI
1
0
0
1
1
X
X
FIGURE 3-4:
EWDS
CS TCSL
CLK
DI
1
0
0
0
0
X
...
X
ORG=VCC, 8 X's ORG=VSS, 9 X'S
(c) 1998 Microchip Technology Inc.
DS21132D-page 7
93C76/86
FIGURE 3-5:
CS
WRITE
STANDBY
CLK ... ...
DI
1
0
1
AN
A0
DN
D0 TCZ
DO
HIGH IMPEDANCE
BUSY
READY
TWC
FIGURE 3-6:
CS
WRAL
STANDBY
CLK ...
DI
1
0
0
0
1
X
...
X
DN
D0 TCZ
DO
ORG=VCC, 8 X's ORG=VSS, 9 X's
HIGH IMPEDANCE
BUSY
READY
Guarantee at Vcc = +4.5V to +5.5V.
TWL
FIGURE 3-7:
CS
ERASE
STANDBY
CLK
DI
1
1
1
AN
...
...
A0 TCZ
DO
HIGH IMPEDANCE BUSY READY
TWC
DS21132D-page 8
(c) 1998 Microchip Technology Inc.
93C76/86
FIGURE 3-8:
CS
ERAL
STANDBY
CLK ...
DI
1
0
0
1
0
X
X TCZ
HIGH IMPEDANCE
DO
BUSY
READY
TEC
ORG=VCC, 8 X's ORG=VSS, 9 X's
Guarantee at VCC = +4.5V to +5.5V.
4.0
4.1
PIN DESCRIPTIONS
Chip Select (CS)
through Table 1-7 for more details). CLK and DI then become don't care inputs waiting for a new start condition to be detected. Note: CS must go LOW between consecutive instructions, except when performing a sequential read (Refer to Section 3.1 for more detail on sequential reads).
A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated will be completed, regardless of the CS input signal. If CS is brought LOW during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be LOW for 250 ns minimum (TCSL) between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status.
4.3
Data In (DI)
Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
4.4
Data Out (DO)
4.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93C76/86. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be continued anytime with respect to clock HIGH time (TCKH) and clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a "Don't Care" if CS is LOW (device deselected). If CS is HIGH, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a start condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all opcode, address, and data bits before an instruction is executed (see Table 1-4
Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available when CS is high. It will be displayed until the next start bit occurs as long as CS stays high.
4.5
Organization (ORG)
When ORG is connected to VCC, the x16 memory organization is selected. When ORG is tied to VSS, the x8 memory organization is selected. There is an internal pull-up resistor on the ORG pin that will select x16 organization when left unconnected.
4.6
Program Enable (PE)
This pin allows the user to enable or disable the ability to write data to the memory array. If the PE pin is floated or tied to VCC, the device can be programmed. If the PE pin is tied to VSS, programming will be inhibited. There is an internal pull-up on this device that enables programming if this pin is left floating.
(c) 1998 Microchip Technology Inc.
DS21132D-page 9
93C76/86
NOTES:
DS21132D-page 10
(c) 1998 Microchip Technology Inc.
93C76/86
93C76/86 Product Identification System
To order or obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales office.
93C76/86
-
\P Package: Temperature Range: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead Blank = 0C to +70C I = -40C to +85C E = -40C to +125C 93C76/86 93C76T/86T Microwire Serial EEPROM Microwire Serial EEPROM (Tape and Reel)
Device:
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com)
(c) 1998 Microchip Technology Inc.
DS21132D-page 11
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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AMERICAS (continued)
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ASIA/PACIFIC (continued)
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11/15/99
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

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